Validation of Proposed Test Set Reduction Hybrid Compaction Schemes for FPGA-Based Designs

Abdul Rafay Khatri

Abstract

Recently, the density and intricacy of Very Large-Scale Integration (VLSI) circuits are grown, and the number of test vectors has increased drastically. Owing to this, the cost of testing is a significant component for consideration. The two main factors that measure the cost of the test are the size of the test vector sets and test data volume. Compression and compaction are the two approaches used to reduce the aforementioned factors. Compaction is a primary process in the test generation procedure, and there are two classes for it, i.e., dynamic and static compaction approaches. In this paper, the author performs testing and obtains the compact test vectors for various FPGA-based designs. The RASP-FIT fault injection testing tool provides the ATPG testing framework. In this paper, the testing is performed on various FPGA benchmark designs written in Verilog HDL, and the results are validated. The ATPG method developed under the RASP-FIT tool contains new hybrid compaction techniques that calculate compaction and fault coverage for the designs. This work is also compared with the previous work and found that the proposed compaction scheme is better at compacting the test vectors.

 

Keywords: compression, dynamic compaction, static compaction, test generation, test vector size.

 

https://doi.org/10.55463/issn.1674-2974.50.1.23


Full Text:

PDF


References


JHA S. Compaction mechanism to reduce test pattern counts and segmented delay fault testing for path delay faults. University of Iowa, 2013.

AHMADY M, and SAYEDI S M. Fault coverage improvement and test vector generation for combinational circuits using spectral analysis. Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE), 2012, 1–5.

KHATRI A R, HAYEK A, and BÖRSCÖK J. ATPG method with a hybrid compaction technique for combinational digital systems. Proceedings of the SAI Computing Conference (SAI), 2016, 924–930.

JHA S, CHANDRASEKAR K, WU W, et al. A Cube-Aware Compaction Method for Scan ATPG. Proceedings of the 27th International Conference on VLSI Design and 13th International Conference on Embedded Systems, 2014, 98–103.

EGGERSGLUB S, SCHMITZ K, KRENZ-BAATH R, and DRECHSLER R Optimization-based multiple target test generation for highly compacted test sets. Proceedings of the 19th IEEE European Test Symposium (ETS), 2014, 1–6.

KHATRI A R, HAYEK A, and BÖRSCÖK J. RASP-FIT: A Fast and Automatic Fault Injection Tool for Code-Modification of FPGA Designs. International Journal of Advanced Computer Science and Applications, 2018, 9(10), 30–40.

KHATRI A R, HAYEK A, and BÖRSCÖK J. Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-Flow Verilog HDL Designs Under the RASP-FIT Tool. Proceedings of the IEEE 16th International Conference on Dependable, Autonomic and Secure Computing, 2018, 544–551.

KHATRI A R. Development, Verification and Analysis of a Fault-Injection Tool for improving Dependability of FPGA Systems. University of Kassel, 2019.

CHEN Y-W, HO Y-H, CHANG C-M, et al. Parallel order ATPG for test compaction. Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2018, 1–4.

POMERANZ I. Test Compaction by Test Removal Under Transparent Scan. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019, 27(2), 496–500.

KAJIHARA S, POMERANZ I, KINOSHITA K, and REDDY S M. Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. Proceedings of the 30th international on Design automation conference (DAC ’93), 1993, 102–106.

REDDY L N, POMERANZ I, and REDDY S M. COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1992, 12(7), 568–574.

TROMP G. Minimal Test Sets for Combinational Circuits. Proceedings of the International Test Conference, 1991, p. 204.

SCHULZ M H, TRISCHLER E, and SARFERT T M. SOCRATES: a highly efficient automatic test pattern generation system. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988, 7(1), 126–137.

KAJIHARA S, POMERANZ I, KINOSHITA K, and REDDY S M. Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995, 14(12), 1496–1504.

POMERANZ I, REDDY S M, and LIN X. Experimental results of forward-looking reverse order fault simulation on industrial circuits with scan. Proceedings of the 10th Asian Test Symposium, 2001, p. 467.

REDDY L N, POMERANZ I, and REDDY S M. ROTCO: a reverse order test compaction technique. Proceedings of the Euro ASIC ’92, 1992, 52242, 189–194.

XIANG D, SUI W, YIN B, and CHENG K. Compact Test Generation With an Influence Input Measure for Launch-On-Capture Transition Fault Testing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2014, 22(9), 1968–1979.

NAVABI Z. Digital System Test and Testable Design. Boston, MA: Springer US, 2011.

EL-MALEH A H, KHURSHEED S S, and SAIT S M. Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation. Proceedings of the 14th Asian Test Symposium (ATS’05), 2005, 378–385.

DIMOPOULOS M, and LINARDIS P. Efficient static compaction of test sequence sets through the application of set covering techniques. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2004, 194–199.

SAHARI M S, A’AIN A K, and GROUT I. A study on the effect of test vector randomness on test length and its fault coverage. Proceedings of the 10th IEEE International Conference on Semiconductor Electronics (ICSE), 2012, 503–506.

KHATRI A R, HAYEK A, and BÖRSCÖK J. Fault Injection and Test Approach for Behavioural Verilog Designs using the Proposed RASP-FIT Tool. International Journal of Advanced Computer Science and Applications, 2019, 10(4), 57–63.

KHATRI A R, HAYEK A, and BÖRSCÖK J. Validation of selecting SP-values for fault models under proposed RASP-FIT tool. Proceedings of the First International Conference on Latest trends in Electrical Engineering and Computing Technologies (INTELLECT), 2017, 1–7.

KHATRI A R. A Technical Guide for the RASP-FIT Tool. International Journal of Advanced Computer Science and Applications, 2019, 10(12), http://dx.doi.org/10.14569/IJACSA.2019.0101279

MIRKHANI S, and ABRAHAM J A. Fast evaluation of test vector set using a simulation-based statistical metric. Proceedings of the IEEE 32nd VLSI Test Symposium (VTS), 2014, 1–6.

HABIB K, SAFAR M, DESSOUKY M, and SALEM A. Don’t care based dynamic test vector compaction in SAT-ATPG. Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014, 213–217.

DUNBAR C, and NEPAL K. Using Platform FPGAs for Fault Emulation and Test-set Generation to Detect Stuck-at Faults. Journal of Computers, 2011, 6(11), 2335–2344.

ZHANG Y. Diagnostic Test Pattern Generation and Fault Simulation for Stuck-at and Transition Faults. Auburn University, 2012.


Refbacks

  • There are currently no refbacks.