Design and Implementation of L-DSP On-chip Debug Circuit

Bai Chuang, Li Fan, Wang Dong

Abstract

 According to the debug requirements of L-DSP, an on-chip debug circuit based on JTAG interface is proposed in this paper, which implements the debug functions such as storage resource access, CPU pipeline control, hardware breakpoint/observation point, and parameter statistics. Compared with the traditional debug mode, the proposed debug circuit realizes the direct transmission of data between peripherals and memory by adding a DT-DMA module, which greatly improves the debug efficiency. The proposed circuit is designed in a 0.18 μm CMOS process with an area of 167 234.76 μm2 and a power consumption of 8.89 mW. And the proposed circuit and L-DSP are verified under the FPGA. The results show that the proposed circuit has complete debug functions and the rate of DT-DMA for transferring debug data is three times faster than that of the CPU.

 

 

Keywords:  debugging,  on-chip debug, JTAG interface,  DT-DMA,  DMA operation


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References


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