A DLL-based 90° Phase-shifter with Schmitt Frequency Selector Scheme

LIANG Chengtuo,LIANG Liping,WANG Zhijun


In order to deal with the problem of harmonic look in the traditional Delay Locked Loop (DLL), a DLL-based 90°phase-shifter with a Schmitt Frequency Selector(SFS) was proposed. The SFS and dual delay lines were employed to achieve wider locking frequency range. In addition, the proposed SFS exhibits high capability of frequency noise suppression, which improves the stability of the proposed phase-shifter. The proposed phase-shifter, fabricated in SMIC 55 nm CMOS technology, occupies an active area of 0.131 mm2 and utilizes a 1.2 V supply voltage. The test results show that the proposed phase-shifter has an operating frequency ranging from 250 to 800 MHz and consumes 5.98 mW at 800 MHz. Furthermore, the measured peak-to-peak and root-mean-square (rms) jitters of 90°phase-shifted clock are 25.9 and 2.8 ps, respectively.



Keywords: Delay Locked Loop(DLL),  frequency selector,  digitally controlled delay line,  90°phase shift

Full Text:



CHUANG C N,LIU S I. A 20 -MHz to 3 -GHz wide -range multiphase delay-locked loop [J] . IEEE Transactions on Circuits and Systems II:Express Briefs,2009,56(11):850—854.

KAZEMINIA S,MOWLOODI S S,HADIDI K. Wide -range 16- phases DLL based on improved dead -zone phase detector and reduced gain charge pump [C]// Iranian Conference on Electrical Engineering (ICEE). Shahid Beheshti University:IEEE,2014: 133—138.

MOON Y H,KONG I S,RYU Y S,et al. A 2.2 -mW 20 -135MHz false -lock -free DLL for display interface in 0.15 m CMOS[J] . IEEE Transactions on Circuits and Systems II:Express Briefs,

JUNG D J,RYU K,PARK J H,DLL with dithering jitter suppression scheme [J] . IEEE Transactions on Very Large Scale intergration (VLSI)Systems, 2016,24(3):1015—1021.

NG H J,FISCHER A,FEGER R,et al. A DLL -supported low phase noise fractional -N PLL with a wideband VCO and highly linear frequency ramp generator[J] . IEEE Transactions on Circuits and Systems I:Regular Papers,2013,60(12):554—558.

YAO Y F,SUN J A,HUOX H,et al. A fast all digital phase-locked loop with high precision TDC [J] . Journal of Hunan University(Natural Sciences),2017,44(8):131—136.(In Chinese)

SHANGGUAN L Q,LIU B A. Design of a delay locked loop for frequency synthesizer[J] . Microelectronics,2007,37(1):72—75.(In Chinese)

YAO C Y,HO Y H,CHIU Y Y,et al. Designing a SAR-based all- digital delay -locked loop with constant acquisition cycles using a resettable delay line [J] . IEEE Transactions on Very Large Scale intergration(VLSI)Systems,2015,23(3):567—574.

LI J. An analog DLL for mobile DDR controller applications[D]. Shanghai:School of Microelectronics,Shanghai Jiao Tong University,2010:60—62.(In Chinese) [10] HUANG K,CAI Z K,CHEN X,et al. A harmonic-free all digital delay -locked loop using an improved fast -locking successive approximation register-controlled scheme[J] . IEICE TransactionsElectron,2009,E92-C(12):1541—1544.

ANYJ,JUNG D H,RYU K,et al. An energy-efficient all-digital time -domain -based CMOS temperature sensor for SoC thermal management [J] . IEEE Transactions on Very Large Scaleintergration(VLSI)Systems,2015,23(8):1508—1517


  • There are currently no refbacks.