Implement of CORDIC Algorithm with a Small Capacity ROM Table

YAO Yafeng, XU Yangyang, HOU Qiang, ZHONG Liang


In order to optimize the implementation delay and hardware resource consumption of the Coordinate Rotation Digital Computer(CORDIC) in pipeline architecture,a new implementation method based on look-up table was proposed,which completely eliminatesd the iterative computation. This method requires only a lower capacity ROM table,as well as a simple shift operation on the output of the ROM table,so that sine wave or cosine wave output with high accuracy can be obtained. Theoretical simulation and practical verification were carried out in Matlab,Modelsim and XILINX ISE,and the results show that this method of CORDIC only requires two clock cycles of processing delay,and the hardware resource consumption is also reduced when compared with other methods. Additionally,the circuit output accuracy and maximum working frequency are also improved at a certain level.



Keywords: coordinate rotation digital calculation(CORDIC),  pipeline architecture,  look-up table,  programmable logic gate array,  digital signal processing

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